supertex inc. supertex inc. www.supertex.com md2131 doc.# dsfp-md2131 c102412 features ? high resolution transmitting waveform ? up to 3.0a push-pull source-driving current ? 230v p-p maximum output, uses two dn2625 fets ? angle vector beamforming i-q switcher matrix ? 8-bit apodization dac and 7.5 angular resolution ? flexible frequency-resolution trade-off ? programmable aperture windowing ? 250mhz maximum sampling rate ? 25mhz ultrasound maximum frequency ? pwm modulation push-pull current source ? focusing phase adjustment & chirp waveform ? fast spi interface ? 2.5v cmos logic interface ? +5.0v single power supply ? low second order harmonic distortions applications ? medical ultrasound imaging transmit beamforming ? high resolution ndt and sonar phase arrays ? hifu transducer phase arrays beamforming and focus scanning ? piezoelectric & mems transducer waveform drivers ? high speed, high voltage, arbitrary waveform generator general description the md2131 is a high-speed, arbitrary waveform, push-pull source driver. it is designed for medical ultrasound imaging and hifu beamforming applications. it also can be used in ndt, sonar and other ultrasound phase-array focusing beamforming applications. the md2131 consists of cmos digital logic input circuits, an 8-bit current dac for waveform amplitude control, and four pwm current-sources. these current sources are constructed with the high-speed, in-phase and quadrature current-switch matrix and the built-in sine and cosine angle-to-vector look-up table. the angular resolution of the vector table is 7.5 o per step, with a total range of 48 steps. there are four logic input signals to control the in-phase and quadrature pwm push-pull current-sources output timing, frequency, cycle in the burst and waveform envelope. the md2131s output stage is designed to drive two dn2625 depletion n-type mosfets. the mosfet drains are connected to a center-tap ultrasound frequency pulse transformer. the secondary winding of the transformer can connect to the ultrasound piezo or capacitive transducer via a cable with a good impendence match. the md2131 has a high-speed, spi- compatible interface to achieve per-scan-line fast updating of the data register for changing the beamforming phase angles and apodization amplitudes. md2131 block diagram high speed ultrasound beamforming source driver +5.0v iq a dgnd agnd c3a ka c1a c3b c2b c1b vref +v ref ia qa ib qb en sdi sdo sck cs ld vll sub vdd +5.0v +2.5v pa xdrc dn2625 pb t1 +3.3v +70-100v v pp gnd kb c2a rfb data latch & control logic level translator dac vector beamforming switch matrix d1 d2 dn2625 +3.3v +5.0v sin/cos table & level translator downloaded from: http:///
2 md2131 supertex inc. www.supertex.com doc.# dsfp-md2131 c102412 operating supply voltages (over operating conditions unless otherwise speciied, v ll = +2.5v, v dd = +5.0v, r fb = 50k, dac = 0, v ref = 2.5v, t a = 25c) sym parameter min typ max units conditions v ll logic supply 2.3 2.5 2.7 v t a = 0 to 70c v dd power supply 4.75 5.00 5.25 v i llq v ll supply current en = 0 - 0.1 1.0 a standby condition i ddq v dd supply current en = 0 - 0.2 1.0 i llen v ll supply current en = 1 - 5.0 20 a f clk = 0, all logic input no transit i dden v dd supply current en = 1 - 5.0 12 ma i ll50 v ll supply current en = 1 - 0.5 3.0 ma f clk = 50mhz, cw, ia, ib, qa, qb = 0 i dd50 v dd supply current en = 1 - 80 - ma en = 1, ia, ib, qa, qb = 50mhz, cw output characteristics (over operating conditions unless otherwise speciied, v ll = +2.5v, v dd = +5.0v, v ref = 2.5v, r fb = 50k, angle = 45 ia = qa = hi or ib = qb = hi of 1s, d% = 0.1%, t a = 25c) sym parameter min typ max units conditions i max-a/b full scale output peak current 2.88 - 3.52 a dac = 255 i oo-a/b output current offset - 0.5 2.0 ma dac = 0 v pa , v pb output voltage range, +10% of i pa/b 5.3 5.8 - v i pa/b = 1.0a 5.0 5.5 - i pa/b = 1.5a 4.5 5.0 - i pa/b = 3.0a output voltage range, -10% of i pa/b - 1.0 1.5 i pa/b = 1.0a - 1.2 1.7 i pa/b = 1.5a - 1.8 2.3 i pa/b = 3.0a pin coniguration package marking md2131llllll yyw w aaaccc l = l ot n um b er yy = year sealed ww = week sealed a = assembler id c = country of origin = ?green? packaging 1 40 package may or may not include the following marks: si or 40-lead qfn (k7) 40-lead qfn (k7) (top view) absolute maximum ratings parameter value v ll , logic supply -0.5v to +3.5v v dd , positive supply -0.5v to +6.0v v pa v pb driver outputs -0.5v to +6.0v v sub , ground 0v operating temperature 0c to +70c storage temperature -65c to +150c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. ordering information part number package option packing MD2131K7-G 40-lead (5x5) qfn 490/tray -g indicates package is rohs compliant (green) typical thermal resistance package ja 40-lead qfn 26 o c/w* * 4x3, 4-layer 1oz 16-via pcb downloaded from: http:///
3 md2131 supertex inc. www.supertex.com doc.# dsfp-md2131 c102412 aperture dac characteristics(over operating conditions unless otherwise speciied, v ll = +3.3v, v dd = +5v, r fb = 50k, t a = 25c) sym parameter min typ max units conditions reso resolution - 8 - bits --- e linear linearity error - 1.0 3.0 % % of fsr e dnl differential nonlinearity error - 0.6 1.0 % % of fsr mon monotonicity - 8 - bits --- v ref external reference voltage 1.25 - 2.5 v --- logic and data input characteristics(over operating conditions unless otherwise speciied, v ll = +3.3v, v dd = +5v, r fb = 50k, t a = 0 - 70c) sym parameter min typ max units conditions v ih input logic high voltage 0.8v ll - v ll v --- v il input logic low voltage 0 - 0.2v ll v --- i ih input logic high current - - 1.0 a --- i il input logic low current -1.0 - - a --- ac electrical characteristics(over operating conditions unless otherwise speciied, v ll = +3.3v, v dd = +5v, r fb = 50k, t a = 25c) sym parameter min typ max units conditions t st dac to output setup time - - 10 s all caps 10nf, dac = 0 to 255, settle to 1lsb t r output current rise time - 2.0 3.0 ns 1.0 resistor load to v dd , dac = 85, angle = 45 o , v ref = 2.5v t f output current fall time - 2.0 3.0 t dr input to output delay on rise - 4.0 5.0 t df input to output delay on fall - 4.0 5.0 t m delay time matching - 2.0 3.0 ns from pa to pb and device to device t j output jitter - 50 - ps --- t 1 sdi valid to sck setup time 0 2.0 - ns see serial interface timing diagram t 2 sdi valid to sck hold time 4.0 - - t 3 sck high time (% of 1/f sck ) 45 - 55 % see serial interface timing diagram t 4 sck low time (% of 1/f sck ) 45 - 55 t 5 cs pulse width 4.0 - 6.0 ns see serial interface timing diagram t 6 lsb sck high to cs high 7.0 - - t 7 cs low to sck high 7.0 - - t 8 sdo propagation delay from sck failing edge - - 10 t 9 cs high to sck raising edge 7.0 - - t 10 cs high to ld raising edge 10 - - f sck serial clock maximum frequency 40 50 - mhz --- thd total harmonic distortion - -45 -40 db --- t en-off en fall to pa/pb turn off time - 5.0 8.0 ns 50% to 90% t en-on en rise to pa/pb turn on time - 13.5 20.0 s 50% to 10% downloaded from: http:///
4 md2131 supertex inc. www.supertex.com doc.# dsfp-md2131 c102412 serial register description command msb dac value register lsb vector angle register c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 a5 a4 a3 a2 a1 a0 command description command description c1 c0 0 0 write to input register 0 1 read register 1 0 power down triggered at c[1:0] = 10 and cs rise edge, other state power-up 1 1 no operation dac input and output description msb dac value register lsb pa/pb output current d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 (0/255)i max-a/b + i oo-a/b 0 0 0 0 0 0 0 1 (1/255)i max-a/b + i oo-a/b 0 1 1 1 1 1 1 1 (127/255)i max-a/b + i oo-a/b 1 0 0 0 0 0 0 0 (128/255)i max-a/b + i oo-a/b 1 1 1 1 1 1 1 0 (254/255)i max-a/b + i oo-a/b 1 1 1 1 1 1 1 1 (255/255)i max-a/b + i oo-a/b angle register and i/q vector description msb angle register lsb angle i-vector (6-bit) q-vector (6-bit) a5 a4 a3 a2 a1 a0 degree cos sin 0 0 0 0 0 0 0 111111 000000 0 0 0 0 0 1 7.5 111110 001000 0 0 0 1 1 0 45 1 101101 101101 0 0 1 1 0 0 90 000000 111111 0 1 0 0 1 0 135 -101101 101101 0 1 1 0 0 0 180 -111111 000000 0 1 1 1 1 0 225 -101101 -101101 1 0 0 1 0 0 270 -000000 -111111 1 0 1 0 1 0 315 101101 -101101 1 0 1 1 1 1 352.5 111110 -001000 1 1 0 0 0 0 360 = 0 2 111111 000000 notes: 1. maximum current magnitude of output pa or pb is at 45 angle, when ia = qa = hi or ib = qb = hi. 2. angle>110000b (48) are reserved states. msb lsb downloaded from: http:///
5 md2131 supertex inc. www.supertex.com doc.# dsfp-md2131 c102412 serial interface timing diagram pwm interface timing diagram 16 sck sdi cs sdo ld t 1 t 2 t 3 t 4 t 5 t 7 t 8 t 6 t 9 t 10 15 3 2 1 -64 -56 -48 -40 -32 -24 -16 -8 0 8 16 24 32 40 48 56 64 in-phase pwm waveforms sample number quadrature pwm waveforms sample number qa qb -64 -56 -48 -40 -32 -24 -16 -8 0 8 16 24 32 40 48 56 64 ia ib downloaded from: http:///
6 md2131 supertex inc. www.supertex.com doc.# dsfp-md2131 c102412 in-phase and quadrature output current equations the in-phase and quadrature phase output sinking current magnitudes, i i and i q , can be calculated by the following equations: i i = 24 ? v ref ? dac ? (2 6 - 1) ? cos() 9 ? r fb i q = 24 ? v ref ? dac ? (2 6 - 1) ? sin() 9 ? r fb where the v ref is the voltage reference, dac is the decimal value of the data in the dac register, r fb is the setting resis - tor value in ohms, and is the value of the vector angle in degrees. the absolute values of the results from the equations rep - resent the magnitude of the output sinking current. the plus or minus sign of the results indicate the current low in to the output port pa or pb, respectively. note that the maximum full scale of pulse current at pa or pb port only can be ob - tained at dac = 255, v ref = 2.5v, r fb = 50k , = 45 and ia = qa = hi or ib = qb = hi conditions. downloaded from: http:///
7 md2131 supertex inc. www.supertex.com doc.# dsfp-md2131 c102412 pin description pin # function description 1 ka kelvin connection a 2 gnd high current output ground 3 c1a bypass cap ka, 10nf low esr x7r ceramic cap 4 gnd high current output ground 5 vdd supplies voltage of the gate driver and internal analog circuit 6 c3a bypass cap to gnd of pin#7, 10nf low esr x7r ceramic cap 7 gnd high current output ground 8 vll supply voltage of logic circuit 9 dgnd digital logic ground 10 sck serial clock input 11 sdi serial data input 12 qa pwm control logic input of quadrature-phase a 13 qb pwm control logic input of quadrature-phase b 14 ia pwm control logic input of in-phase a 15 ib pwm control logic input of in-phase b 16 vdd supplies voltage of the gate driver and internal analog circuit 17 agnd analog reference ground 18 sdo serial data output, updated at sck falling edge 19 cs serial chip select, active low, and buffer register loading clock on rising edge 20 ld dac data register loading clock on rising edge 21 en enable, en = low, pa = pb = hi-z 22 vref external reference voltage input 23 rfb resistor to gnd, 50k 0.1% for the best accuracy 24 gnd high current output ground 25 c3b bypass cap to gnd of pin#24, 10nf low esr x7r ceramic cap 26 vdd supplies voltage of the gate driver and internal analog circuit 27 gnd high current output ground 28 c1b bypass cap to kb, 10nf low esr x7r ceramic cap 29 gnd high current output ground 30 kb kelvin connection b 31 c2b bypass cap to kb, 10nf low esr x7r ceramic cap 32 pb current sinking source driver output b, external schottky diode to vdd 33 pb current sinking source driver output b, external schottky diode to vdd 34 pb current sinking source driver output b, external schottky diode to vdd 35 vsub substrate voltage must connected to the lowest potential of the ic, the ground 3637 pa current sinking source driver output a, external schottky diode to vdd 38 pa current sinking source driver output a, external schottky diode to vdd 39 pa current sinking source driver output a, external schottky diode to vdd 40 c2a bypass cap to ka, 10nf low esr x7r ceramic cap notes: 1. pins #35 & #36 are vsub connected to the center thermal pad internally in the package. 2. all bypass capacitors need be very close to the pins downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry an d specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//ww w. supertex.com ) ?2012 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 8 md2131 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-md2131 c102412 40-lead qfn package outline (k7) 5.00x5.00mm body, 0.80mm height (max), 0.40mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.70 0.00 0.20 ref 0.15 4.85* 3.45 4.85* 3.45 0.40 bsc 0.25 ? 0.00 0 o nom 0.75 0.02 0.20 5.00 3.60 5.00 3.60 0.35 ? - - max 0.80 0.05 0.25 5.15* 3.70 ? 5.15* 3.70 ? 0.45 ? 0.15 14 o jedec registration mo-220, variation whhe-1, issue k, june 2006 * this dimension is not speciied in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc. #: dspd-40qfnk75x5p040, version c041009. notes: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. seating plane top vi ew side view bottom view view b vi ew b 1 note 3 note 2 40 1 40 d e d2 e2 note 1 (index area d/2 x e/2) note 1 (index area d/2 x e/2) e b l l1 a a1 a3 downloaded from: http:///
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